1. Field of the Invention
The present invention relates to a method of forming wires in a semiconductor device; and more particularly, to a method of forming silicide wires in a semiconductor device, in which operating speed can be improved by increasing the thickness of the silicide wire.
2. Description of the Related Art
Silicide films are commonly applied in semiconductor devices for reducing contact resistance with polysilicon materials, for example polysilicon materials found in source and drain regions of a device The use of cobalt silicide film has recently become popular for this purpose. It is preferable to form the cobalt silicide film in a bi-layer system composed of a silicon surface and a cobalt film, wherein the silicon surface has a crystal structure that is compatible with the cobalt silicide film. Further, the cobalt film is formed by an initial deposition of a capping layer made of Ti, TiW or TiN prior to cobalt reaction. The capping layer improves the electrical characteristics of the device and mitigates excessive oxidation of the cobalt. An example of a Ti capping layer is disclosed in U.S. Pat. No. 5,736,461, illustrating a process for preventing cobalt oxidation during silicide formation.
In a typical cobalt silicide film process, the cobalt silicide film of uniform thickness is formed on a source region, a drain region, and a polysilicon gate region of a semiconductor device. Since the thickness of the silicide film plays an important role in the performance of the resulting semiconductor device, two separate semiconductor devices having mutually different junction depths between source and drain regions can be provided in a single integrated circuit. In other words, in a semiconductor device having a relatively shallow source and drain junction depth it is required to form a comparatively shallow cobalt silicide film on the source and drain regions in order to reduce the risk of a xe2x80x9cspikingxe2x80x9d phenomenon. In a semiconductor device having a relatively deep junction depth it is required to form a comparatively thick cobalt silicide film on regions having the deep junction depth in order to reduce contact resistance.
FIGS. 1 and 2 are sectional views formation of silicide wiring in a conventional semiconductor device.
With reference to FIG. 1, in a semiconductor substrate 10, a device separation region 14 and a wire separation region 12 are formed in a trench isolation process. The trenches are filled with a dielectric material according to standard practices. The device separation region 14 is provided in order to isolate separate respective devices, and the wire separation region 12 isolates respective wires. Subsequently, ion implantation of a device channel is performed, and the top of the resultant structure is coated with polysilicon to form a polysilicon 22 gate structure that is pattered via a photo etching process. Next, appropriate ion implantation is performed. A gate spacer 20 is then formed, and a deep source/drain ion implantation is performed. On the resultant structure, material of Co, Ti or Ni etc. 24 is deposited, and then material nonreactive to a silicidation, such as TiN is deposited 26.
With reference to FIG. 2, following this, silicide reaction is performed in a thermal process, to thus form silicide films 16, 18, 28 in the device region 100 and the wiring region 200. At this time, in the device region 100, silicide films 16, 18 are formed on regions where source and drain of a transistor will be formed, and silicide film 28 is formed on a gate electrode 22. In the wiring region 200, a silicide film 28 is formed on structure 22A, which serves as a wire.
In the conventional wiring method, the semiconductor process continues to strive toward gate lengths of ever-decreasing size, and, as a result, gate thickness also continues to decrease. As a result, the thickness of the silicide for reducing gate resistance becomes thinner while the junction depth becomes shallower. Consequently, the wiring resistance of the gate poly is increased and the operating speed of the resulting device is therefore reduced due to increased RC delay.
It is therefore an object of the present invention to provide a method of forming silicide wires in a semiconductor device, in which a wiring resistance can be reduced and in which operating speed can be improved by thickening the gate silicide for a gate structure that is used as a wire in the semiconductor device.
Another object of the present invention is to provide a method of forming silicide wires in a semiconductor device, in which performance can be improved by reduction of resistance between a drain and source by using two transistors including a gate poly having mutually different thicknesses and a silicide layer having mutually different thicknesses, in the event that transistors are required that exhibit different input/output voltages and internal operating voltages.
In one aspect, the present invention is directed to a method of forming silicide contacts in a semiconductor device. A gate film and a gate spacer are formed on a substrate in a device region and a wiring region of the substrate. A first metal film reactive to silicide and a reactive barrier film are sequentially formed on the resultant structure. Photoresist is deposited on the device region, the reactive barrier film of the wiring region is therefore exposed. The exposed reactive barrier film is removed and, the photoresist is removed. A second metal film reactive to the silicide is formed on the resultant structure. A silicide reaction is performed on the resultant structure, thereby providing a first silicide film formed on the gate film of the wiring region that is greater in thickness than a second silicide film formed on the gate film of the device region.
The reactive barrier film may comprise, for example, TiN. The first and second metal films may comprise, for example, Co, Ti, or Ni
In an optional embodiment, the reacting and non-reacting residuals are removed in a cleaning process after performing the silicide reaction. The silicide reaction may comprise a rapid thermal process.
The reactive barrier film is exposed by eliminating the photoresist formed on the wiring region while retaining the photoresist formed on the device region, through a photolithography process.
The gate film of the wiring region may comprise, for example, an interconnect wire, or a transistor gate.
In another aspect, the present invention is directed to a method of forming silicide wires in a semiconductor device. A gate film and a gate spacer are formed on a substrate in a device region and a wiring region of the substrate. A first metal film reactive to silicide and a reactive barrier film on the resultant structure are sequentially formed. Photoresist is deposited on the reactive barrier film. The photoresist formed on the wiring region is then removed so as to expose the reactive barrier film in the wiring region. The exposed reactive barrier film is removed and the photoresist in the device region is removed. A second metal film reactive to silicide on the resultant structure is formed after removing the photoresist in the device region. A silicide reaction is performed on the resultant structure, thereby providing a first silicide film formed on the gate film of the wiring region that is greater in thickness that a second silicide film formed on the gate film of the device region.